| Title: |
Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node |
| Authors: |
Sakhare, S.; Perumkunnil, M.; Bao, T. Huynh; Rao, S.; Kim, W.; Crotti, D.; Yasin, F.; Couet, S.; Swerts, J.; Kundu, S.; Yakimets, D.; Baert, R.; Oh, HR.; Spessot, A.; Mocuta, A.; Kar, G. Sankar; Furnemont, A. |
| Source: |
2018 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2018 IEEE International. :18.3.1-18.3.4 Dec, 2018 |
| Relation: |
2018 IEEE International Electron Devices Meeting (IEDM) |
| Database: |
IEEE Xplore Digital Library |