| Title: |
Three-Layer BEOL Process Integration with Supervia and Self-Aligned-Block Options for the 3 nm Node |
| Authors: |
Vega-Gonzalez, V.; Wilson, C. J.; Briggs, B.; Decoster, S.; Versluijs, J.; Lesniewska, A.; Paolillo, S.; Baert, R.; Puliyalil, H.; Bekaert, J.; Kesters, E.; Le, Q. T.; Lorant, C.; Varela P., O.; Teugels, L.; Heylen, N.; El-Mekki, Z.; van der Veen, M.; Webers, T.; Vats, H.; Rynders, L.; Cupak, M.; Uk-Lee, J.; Drissi, Y.; Halipre, L.; Charley, A.-L.; Verdonck, P.; Witters, T.; Gompel, S. V.; Kimura, Y.; Jourdan, N.; Ciofi, I.; Gupta, A.; Contino, A.; Boccardi, G.; Lariviere, S.; Dupas, L.; De-Wachter, B.; Vancoille, E.; Lazzarino, F.; Ercken, M; Debacker, P.; Kim, R.; Trivkovic, D.; Croes, K.; Leray, P.; Dillemans, L.; Chen, Y.-F.; Tokei, Z. |
| Source: |
2019 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2019 IEEE International. :19.3.1-19.3.4 Dec, 2019 |
| Relation: |
2019 IEEE International Electron Devices Meeting (IEDM) |
| Database: |
IEEE Xplore Digital Library |