Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects With Metal Vias
| Title: | Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects With Metal Vias |
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| Authors: | Agashiwala, K.; Jiang, J.; Parto, K.; Zhang, D.; Yeh, C.; Banerjee, K. |
| Source: | IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 68(4):2083-2091 Apr, 2021 |
| Database: | IEEE Xplore Digital Library |