All-Digital Closed-Loop Unified Retention/Wake-Up Clamp in a 10nm 4-Core x86 IP
| Title: | All-Digital Closed-Loop Unified Retention/Wake-Up Clamp in a 10nm 4-Core x86 IP |
|---|---|
| Authors: | Augustine, C.; Afzal, A.; Misgar, U.; Owahid, A.; Raman, A.; Subramanian, K.; Merchant, F.; Tschanz, J.; Khellah, M. |
| Source: | 2021 Symposium on VLSI Circuits VLSI Circuits, 2021 Symposium on. :1-2 Jun, 2021 |
| Relation: | 2021 Symposium on VLSI Circuits |
| Database: | IEEE Xplore Digital Library |