Scalable Resonant Power Clock Generation for Adiabatic Logic Design
| Title: | Scalable Resonant Power Clock Generation for Adiabatic Logic Design |
|---|---|
| Authors: | Kuttappa, Ragh; Filippini, Leo; Sica, Nicholas; Taskin, Baris |
| Source: | 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) ISVLSI VLSI (ISVLSI), 2021 IEEE Computer Society Annual Symposium on. :338-342 Jul, 2021 |
| Relation: | 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
| Database: | IEEE Xplore Digital Library |