An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS
| Title: | An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS |
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| Authors: | Li, Ziyu; Shan, Weiwei; Wu, Chengjun; Ge, Haitao; Yang, Jun |
| Source: | 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Solid-State Circuits Conference (A-SSCC), 2021 IEEE Asian. :1-3 Nov, 2021 |
| Relation: | 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) |
| Database: | IEEE Xplore Digital Library |