| Title: |
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part I: CNFET Transistor Optimization |
| Authors: |
Chen, R.; Chen, L.; Liang, J.; Cheng, Y.; Elloumi, S.; Lee, J.; Xu, K.; Georgiev, V.P.; Ni, K.; Debacker, P.; Asenov, A.; Todri-Sanial, A. |
| Source: |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 30(4):432-439 Apr, 2022 |
| Database: |
IEEE Xplore Digital Library |