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Deriving Pipeline Models for Timing Analysis from High-Level HDL Processor Designs

Title:	Deriving Pipeline Models for Timing Analysis from High-Level HDL Processor Designs
Authors:	Bensaid, Samira Ait; Asavoae, Mihail; Thabet, Farhat; Jan, Mathieu
Source:	2022 20th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) Formal Methods and Models for System Design (MEMOCODE), 2022 20th ACM-IEEE International Conference on. :1-8 Oct, 2022
Relation:	2022 20th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Database:	IEEE Xplore Digital Library