A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers
| Title: | A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers |
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| Authors: | Nummer, Muhammad; Sachdev, Manoj |
| Source: | Journal of Electronic Testing: Theory and Applications. June 2003 19(3):299-314 |
| Database: | Springer Nature Journals |