Reuse methodology manual for system-on-a-chip designs

• Foreword
• p. xiii

• Preface to the Third Edition
• p. xv

• Acknowledgements
• p. xvii

• 1
• Introduction
• p. 1

• 1.1
• Goals of This Manual
• p. 2

• 1.1.1
• Assumptions
• p. 3

• 1.1.2
• Definitions
• p. 3

• 1.1.3
• Virtual Socket Interface Alliance
• p. 4

• 1.2
• Design for Reuse: The Challenge
• p. 4

• 1.2.1
• Design for Use
• p. 5

• 1.2.2
• Design for Reuse
• p. 5

• 1.3
• The Emerging Business Model for Reuse
• p. 6

• 2
• The System-on-Chip Design Process
• p. 9

• 2.1
• A Canonical SoC Design
• p. 9

• 2.2
• System Design Flow
• p. 11

• 2.2.1
• Waterfall vs. Spiral
• p. 11

• 2.2.2
• Top-Down vs. Bottom-Up
• p. 15

• 2.2.3
• Construct by Correction
• p. 15

• 2.2.4
• Summary
• p. 16

• 2.3
• The Specification Problem
• p. 17

• 2.3.1
• Specification Requirements
• p. 17

• 2.3.2
• Types of Specifications
• p. 18

• 2.4
• The System Design Process
• p. 19

• 3
• System-Level Design Issues: Rules and Tools
• p. 23

• 3.1
• The Standard Model
• p. 23

• 3.1.1
• Soft IP vs. Hard IP
• p. 25

• 3.1.2
• The Role of Full-Custom Design in Reuse
• p. 27

• 3.2
• Design for Timing Closure: Logic Design Issues
• p. 28

• 3.2.1
• Interfaces and Timing Closure
• p. 28

• 3.2.2
• Synchronous vs. Asynchronous Design Style
• p. 33

• 3.2.3
• Clocking
• p. 35

• 3.2.4
• Reset
• p. 36

• 3.2.5
• Timing Exceptions and Multicycle Paths
• p. 37

• 3.3
• Design for Timing Closure: Physical Design Issues
• p. 38

• 3.3.1
• Floorplanning
• p. 38

• 3.3.2
• Synthesis Strategy and Timing Budgets
• p. 39

• 3.3.3
• Hard Macros
• p. 39

• 3.3.4
• Clock Distribution
• p. 40

• 3.4
• Design for Verification: Verification Strategy
• p. 40

• 3.5
• System Interconnect and On-Chip Buses
• p. 42

• 3.5.1
• Basic Interface Issues
• p. 43

• 3.5.2
• Tristate vs. Mux Buses
• p. 47

• 3.5.3
• Synchronous Design of Buses
• p. 47

• 3.5.4
• Summary
• p. 47

• 3.5.5
• IP-to-IP Interfaces
• p. 48

• 3.6
• Design for Bring-Up and Debug: On-Chip Debug Structures
• p. 51

• 3.7
• Design for Low Power
• p. 52

• 3.7.1
• Lowering the Supply Voltage
• p. 53

• 3.7.2
• Reducing Capacitance and Switching Activity
• p. 54

• 3.7.3
• Sizing and Other Synthesis Techniques
• p. 56

• 3.7.4
• Summary
• p. 57

• 3.8
• Design for Test: Manufacturing Test Strategies
• p. 57

• 3.8.1
• System-Level Test Issues
• p. 57

• 3.8.2
• Memory Test
• p. 58

• 3.8.3
• Microprocessor Test
• p. 58

• 3.8.4
• Other Macros
• p. 59

• 3.8.5
• Logic BIST
• p. 59

• 3.9
• Prerequisites for Reuse
• p. 60

• 3.9.1
• Libraries
• p. 60

• 3.9.2
• Physical Design Rules
• p. 61

• 4
• The Macro Design Process
• p. 63

• 4.1
• Overview of IP Design
• p. 63

• 4.1.1
• Characteristics of Good IP
• p. 64

• 4.1.2
• Implementation and Verification IP
• p. 65

• 4.1.3
• Overview of Design Process
• p. 67

• 4.2
• Key Features
• p. 68

• 4.3
• Planning and Specification
• p. 69

• 4.3.1
• Functional Specification
• p. 69

• 4.3.2
• Verification Specification
• p. 71

• 4.3.3
• Packaging Specification
• p. 71

• 4.3.4
• Development Plan
• p. 71

• 4.3.5
• High-Level Models as Executable Specifications
• p. 72

• 4.4
• Macro Design and Verification
• p. 73

• 4.4.1
• Summary
• p. 77

• 4.5
• Soft Macro Productization
• p. 78

• 4.5.1
• Productization Process
• p. 78

• 4.5.2
• Activities and Tools
• p. 78

• 5
• RTL Coding Guidelines
• p. 81

• 5.1
• Overview of the Coding Guidelines
• p. 81

• 5.2
• Basic Coding Practices
• p. 82

• 5.2.1
• General Naming Conventions
• p. 82

• 5.2.2
• Naming Conventions for VITAL Support
• p. 84

• 5.2.3
• State Variable Names
• p. 85

• 5.2.4
• Include Informational Headers in Source Files
• p. 85

• 5.2.5
• Use Comments
• p. 87

• 5.2.6
• Keep Commands on Separate Lines
• p. 87

• 5.2.7
• Line Length
• p. 87

• 5.2.8
• Indentation
• p. 88

• 5.2.9
• Do Not Use HDL Reserved Words
• p. 89

• 5.2.10
• Port Ordering
• p. 89

• 5.2.11
• Port Maps and Generic Maps
• p. 92

• 5.2.12
• VHDL Entity, Architecture, and Configuration Sections
• p. 93

• 5.2.13
• Use Functions
• p. 93

• 5.2.14
• Use Loops and Arrays
• p. 94

• 5.2.15
• Use Meaningful Labels
• p. 96

• 5.3
• Coding for Portability
• p. 97

• 5.3.1
• Use Only IEEE Standard Types (VHDL)
• p. 97

• 5.3.2
• Do Not Use Hard-Coded Numeric Values
• p. 98

• 5.3.3
• Packages (VHDL)
• p. 98

• 5.3.4
• Constant Definition Files (Verilog)
• p. 98

• 5.3.5
• Avoid Embedding Synthesis Commands
• p. 99

• 5.3.6
• Use Technology-Independent Libraries
• p. 99

• 5.3.7
• Coding For Translation
• p. 100

• 5.4
• Guidelines for Clocks and Resets
• p. 101

• 5.4.1
• Avoid Mixed Clock Edges
• p. 102

• 5.4.2
• Avoid Clock Buffers
• p. 103

• 5.4.3
• Avoid Gated Clocks
• p. 103

• 5.4.4
• Avoid Internally Generated Clocks
• p. 104

• 5.4.5
• Gated Clocks and Low-Power Designs
• p. 105

• 5.4.6
• Avoid Internally Generated Resets
• p. 106

• 5.4.7
• Reset Logic Function
• p. 107

• 5.4.8
• Single-Bit Synchronizers
• p. 108

• 5.4.9
• Multiple-Bit Synchronizers
• p. 108

• 5.5
• Coding for Synthesis
• p. 108

• 5.5.1
• Infer Registers
• p. 109

• 5.5.2
• Avoid Latches
• p. 110

• 5.5.3
• If you must use a latch
• p. 113

• 5.5.4
• Avoid Combinational Feedback
• p. 113

• 5.5.5
• Specify Complete Sensitivity Lists
• p. 114

• 5.5.6
• Blocking and Nonblocking Assignments (Verilog)
• p. 117

• 5.5.7
• Signal vs. Variable Assignments (VHDL)
• p. 119

• 5.5.8
• Case Statements vs. if-then-else Statements
• p. 120

• 5.5.9
• Coding Sequential Logic
• p. 122

• 5.5.10
• Coding Critical Signals
• p. 124

• 5.5.11
• Avoid Delay Times
• p. 124

• 5.5.12
• Avoid ful_case and parallel_case Pragmas
• p. 124

• 5.6
• Partitioning for Synthesis
• p. 125

• 5.6.1
• Register All Outputs
• p. 125

• 5.6.2
• Locate Related Combinational Logic in a Single Module
• p. 126

• 5.6.3
• Separate Modules That Have Different Design Goals
• p. 127

• 5.6.4
• Asynchronous Logic
• p. 128

• 5.6.5
• Arithmetic Operators: Merging Resources
• p. 128

• 5.6.6
• Partitioning for Synthesis Runtime
• p. 130

• 5.6.7
• Avoid Timing Exceptions
• p. 130

• 5.6.8
• Eliminate Glue Logic at the Top Level
• p. 133

• 5.6.9
• Chip-Level Partitioning
• p. 134

• 5.7
• Designing with Memories
• p. 135

• 5.8
• Code Profiling
• p. 136

• 6
• Macro Synthesis Guidelines
• p. 137

• 6.1
• Overview of the Synthesis Problem
• p. 137

• 6.2
• Macro Synthesis Strategy
• p. 138

• 6.2.1
• Macro Timing Constraints
• p. 139

• 6.2.2
• Subblock Timing Constraints
• p. 139

• 6.2.3
• Synthesis in the Design Process
• p. 140

• 6.2.4
• Subblock Synthesis Process
• p. 141

• 6.2.5
• Macro Synthesis Process
• p. 141

• 6.2.6
• Wire Load Models
• p. 142

• 6.2.7
• Preserve Clock and Reset Networks
• p. 142

• 6.2.8
• Code Checking Before Synthesis
• p. 143

• 6.2.9
• Code Checking After Synthesis
• p. 143

• 6.3
• Physical Synthesis
• p. 144

• 6.3.1
• Classical Synthesis
• p. 144

• 6.3.2
• Physical Synthesis
• p. 145

• 6.3.3
• Physical Synthesis Deliverables
• p. 145

• 6.4
• RAM and Datapath Generators
• p. 145

• 6.4.1
• Memory Design
• p. 146

• 6.4.2
• RAM Generator Flow
• p. 147

• 6.4.3
• Datapath Design
• p. 148

• 6.5
• Coding Guidelines for Synthesis Scripts
• p. 150

• 7
• Macro Verification Guidelines
• p. 153

• 7.1
• Overview of Macro Verification
• p. 153

• 7.1.1
• Verification Plan
• p. 154

• 7.1.2
• Verification Strategy
• p. 155

• 7.2
• Inspection as Verification
• p. 159

• 7.3
• Adversarial Testing
• p. 160

• 7.4
• Testbench Design
• p. 161

• 7.4.1
• Transaction-Based Verification
• p. 161

• 7.4.2
• Component-Based Verification
• p. 163

• 7.4.3
• Automated Response Checking
• p. 165

• 7.4.4
• Verification Suite Design
• p. 166

• 7.5
• Design of Verification Components
• p. 169

• 7.5.1
• Bus Functional Models
• p. 169

• 7.5.2
• Monitors
• p. 171

• 7.5.3
• Device Models
• p. 171

• 7.5.4
• Verification Component Usage
• p. 172

• 7.6
• Getting to 100%
• p. 172

• 7.6.1
• Functional and Code Coverage
• p. 172

• 7.6.2
• Prototyping
• p. 172

• 7.6.3
• Limited Production
• p. 173

• 7.6.4
• Property Checking
• p. 173

• 7.6.5
• Code Coverage Analysis
• p. 174

• 7.7
• Timing Verification
• p. 177

• 8
• Developing Hard Macros
• p. 179

• 8.1
• Overview
• p. 179

• 8.1.1
• Why and When to Use Hard Macros
• p. 180

• 8.1.2
• Design Process for Hard vs. Soft Macros
• p. 181

• 8.2
• Design Issues for Hard Macros
• p. 181

• 8.2.1
• Full-Custom Design
• p. 181

• 8.2.2
• Interface Design
• p. 182

• 8.2.3
• Design For Test
• p. 183

• 8.2.4
• Clock
• p. 184

• 8.2.5
• Aspect Ratio
• p. 185

• 8.2.6
• Porosity
• p. 186

• 8.2.7
• Pin Placement and Layout
• p. 187

• 8.2.8
• Power Distribution
• p. 187

• 8.2.9
• Antenna Checking
• p. 188

• 8.3
• The Hard Macro Design Process
• p. 190

• 8.4
• Productization of Hard Macros
• p. 190

• 8.4.1
• Physical Design
• p. 190

• 8.4.2
• Verification
• p. 193

• 8.5
• Model Development for Hard Macros
• p. 194

• 8.5.1
• Functional Models
• p. 194

• 8.5.2
• Timing Models
• p. 199

• 8.5.3
• Power Models
• p. 200

• 8.5.4
• Test Models
• p. 201

• 8.5.5
• Physical Models
• p. 204

• 8.6
• Porting Hard Macros
• p. 204

• 9
• Macro Deployment: Packaging for Reuse
• p. 207

• 9.1
• Delivering the Complete Product
• p. 207

• 9.1.1
• Soft Macro Deliverables
• p. 208

• 9.1.2
• Hard Macro Deliverables
• p. 210

• 9.1.3
• Software
• p. 212

• 9.1.4
• The Design Archive
• p. 213

• 9.2
• Contents of the User Guide
• p. 214

• 10
• System Integration with Reusable Macros
• p. 217

• 10.1
• Integration Overview
• p. 217

• 10.2
• Integrating Macros into an SoC Design
• p. 218

• 10.2.1
• Problems in Integrating IP
• p. 218

• 10.2.2
• Strategies for Managing Interfacing Issues
• p. 219

• 10.2.3
• Interfacing Hard Macros to the Rest of the Design
• p. 220

• 10.3
• Selecting IP
• p. 221

• 10.3.1
• Hard Macro Selection
• p. 221

• 10.3.2
• Soft Macro Selection
• p. 221

• 10.3.3
• Soft Macro Installation
• p. 222

• 10.3.4
• Soft Macro Configuration
• p. 223

• 10.3.5
• Synthesis of Soft Macros
• p. 223

• 10.4
• Integrating Memories
• p. 223

• 10.5
• Physical Design
• p. 224

• 10.5.1
• Design Planning and Synthesis
• p. 226

• 10.5.2
• Physical Placement
• p. 230

• 10.5.3
• Timing Closure
• p. 234

• 10.5.4
• Verifying the Physical Design
• p. 237

• 10.5.5
• Summary
• p. 238

• 11
• System-Level Verification Issues
• p. 239

• 11.1
• The Importance of Verification
• p. 239

• 11.2
• The Verification Strategy
• p. 240

• 11.3
• Interface Verification
• p. 241

• 11.3.1
• Transaction Verification
• p. 241

• 11.3.2
• Data or Behavioral Verification
• p. 242

• 11.3.3
• Standardized Interfaces
• p. 244

• 11.4
• Functional Verification
• p. 244

• 11.5
• Random Testing
• p. 247

• 11.6
• Application-Based Verification
• p. 249

• 11.6.1
• Software-Driven Application Testbench
• p. 250

• 11.6.2
• Rapid Prototyping for Testing
• p. 251

• 11.7
• Gate-Level Verification
• p. 253

• 11.7.1
• Sign-Off Simulation
• p. 253

• 11.7.2
• Formal Verification
• p. 254

• 11.7.3
• Gate-Level Simulation with Full Timing
• p. 255

• 11.8
• Specialized Hardware for System Verification
• p. 256

• 11.8.1
• Accelerated Verification Overview
• p. 258

• 11.8.2
• RTL Acceleration
• p. 259

• 11.8.3
• Software Driven Verification
• p. 260

• 11.8.4
• Traditional In-Circuit Verification
• p. 260

• 11.8.5
• Design Guidelines for Emulation
• p. 261

• 11.8.6
• Testbenches for Emulation
• p. 261

• 12
• Data and Project Management
• p. 265

• 12.1
• Data Management
• p. 265

• 12.1.1
• Revision Control Systems
• p. 265

• 12.1.2
• Bug Tracking
• p. 267

• 12.1.3
• Regression Testing
• p. 267

• 12.1.4
• Managing Multiple Sites
• p. 267

• 12.1.5
• Archiving
• p. 268

• 12.2
• Project Management
• p. 269

• 12.2.1
• Development Process
• p. 269

• 12.2.2
• Functional Specification
• p. 269

• 12.2.3
• Project Plan
• p. 270

• 13
• Implementing Reuse-Based SoC Designs
• p. 271

• 13.1
• Alcatel
• p. 272

• 13.2
• Atmel
• p. 274

• 13.3
• Infineon Technologies
• p. 276

• 13.4
• LSI Logic
• p. 278

• 13.5
• Philips Semiconductor
• p. 280

• 13.6
• STMicroelectronics
• p. 282

• 13.7
• Conclusion
• p. 284

• Bibliography
• p. 285

• Index
• p. 287